Investigation on Ge(0.8)Si(0.2)-Selective Atomic Layer Wet-Etching of Ge for Vertical Gate-All-Around Nanodevice

For the formation of nano-scale Ge channels in vertical Gate-all-around field-effect transistors (vGAAFETs), the selective isotropic etching of Ge selective to Ge(0.8)Si(0.2) was considered. In this work, a dual-selective atomic layer etching (ALE), including Ge(0.8)Si(0.2)-selective etching of Ge and crystal-orientation selectivity of Ge oxidation, has been developed to control the etch rate and the size of the Ge nanowires. The ALE of Ge in p(+)-Ge(0.8)Si(0.2)/Ge stacks with 70% HNO(3) as oxidizer and deionized (DI) water as oxide-removal was investigated in detail. The saturated relative etched amount per cycle (REPC) and selectivity at different HNO(3) temperatures between Ge and p(+)-Ge(0.8)Si(0.2) were obtained. In p(+)-Ge(0.8)Si(0.2)/Ge stacks with (110) sidewalls, the REPC of Ge was 3.1 nm and the saturated etching selectivity was 6.5 at HNO(3) temperature of 20 °C. The etch rate and the selectivity were affected by HNO(3) temperatures. As the HNO(3) temperature decreased to 10 °C, the REPC of Ge was decreased to 2 nm and the selectivity remained at about 7.4. Finally, the application of ALE in the formation of Ge nanowires in vGAAFETs was demonstrated where the preliminary I(d)–V(ds) output characteristic curves of Ge vGAAFET were provided.