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Semiconductor Chip Electrical Interconnection and Bonding by Nano-Locking with Ultra-Fine Bond-Line Thickness

The potential of an innovation for establishing a simultaneous mechanical, thermal, and electrical connection between two metallic surfaces without requiring a prior time-consuming and expensive surface nanoscopic planarization and without requiring any intermediate conductive material has been expl...

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Autores principales: Guo, Jielin, Shih, Yu-Chou, Sheikhi, Roozbeh, You, Jiun-Pyng, Shi, Frank G.
Formato: Online Artículo Texto
Lenguaje:English
Publicado: MDPI 2021
Materias:
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC8401537/
https://www.ncbi.nlm.nih.gov/pubmed/34443732
http://dx.doi.org/10.3390/nano11081901
_version_ 1783745574450757632
author Guo, Jielin
Shih, Yu-Chou
Sheikhi, Roozbeh
You, Jiun-Pyng
Shi, Frank G.
author_facet Guo, Jielin
Shih, Yu-Chou
Sheikhi, Roozbeh
You, Jiun-Pyng
Shi, Frank G.
author_sort Guo, Jielin
collection PubMed
description The potential of an innovation for establishing a simultaneous mechanical, thermal, and electrical connection between two metallic surfaces without requiring a prior time-consuming and expensive surface nanoscopic planarization and without requiring any intermediate conductive material has been explored. The method takes advantage of the intrinsic nanoscopic surface roughness on the interconnecting surfaces: the two surfaces are locked together for electrical interconnection and bonding with a conventional die bonder, and the connection is stabilized by a dielectric adhesive filled into nanoscale valleys on the interconnecting surfaces. This “nano-locking” (NL) method for chip interconnection and bonding is demonstrated by its application for the attachment of high-power GaN-based semiconductor dies to its device substrate. The bond-line thickness of the present NL method achieved is under 100 nm and several hundred times thinner than those achieved using mainstream bonding methods, resulting in a lower overall device thermal resistance and reduced electrical resistance, and thus an improved overall device performance and reliability. Different bond-line thickness strongly influences the overall contact area between the bonding surfaces, and in turn results in different contact resistance of the packaged devices enabled by the NL method and therefore changes the device performance and reliability. The present work opens a new direction for scalable, reliable, and simple nanoscale off-chip electrical interconnection and bonding for nano- and micro-electrical devices. Besides, the present method applies to the bonding of any surfaces with intrinsic or engineered surface nanoscopic structures as well.
format Online
Article
Text
id pubmed-8401537
institution National Center for Biotechnology Information
language English
publishDate 2021
publisher MDPI
record_format MEDLINE/PubMed
spelling pubmed-84015372021-08-29 Semiconductor Chip Electrical Interconnection and Bonding by Nano-Locking with Ultra-Fine Bond-Line Thickness Guo, Jielin Shih, Yu-Chou Sheikhi, Roozbeh You, Jiun-Pyng Shi, Frank G. Nanomaterials (Basel) Article The potential of an innovation for establishing a simultaneous mechanical, thermal, and electrical connection between two metallic surfaces without requiring a prior time-consuming and expensive surface nanoscopic planarization and without requiring any intermediate conductive material has been explored. The method takes advantage of the intrinsic nanoscopic surface roughness on the interconnecting surfaces: the two surfaces are locked together for electrical interconnection and bonding with a conventional die bonder, and the connection is stabilized by a dielectric adhesive filled into nanoscale valleys on the interconnecting surfaces. This “nano-locking” (NL) method for chip interconnection and bonding is demonstrated by its application for the attachment of high-power GaN-based semiconductor dies to its device substrate. The bond-line thickness of the present NL method achieved is under 100 nm and several hundred times thinner than those achieved using mainstream bonding methods, resulting in a lower overall device thermal resistance and reduced electrical resistance, and thus an improved overall device performance and reliability. Different bond-line thickness strongly influences the overall contact area between the bonding surfaces, and in turn results in different contact resistance of the packaged devices enabled by the NL method and therefore changes the device performance and reliability. The present work opens a new direction for scalable, reliable, and simple nanoscale off-chip electrical interconnection and bonding for nano- and micro-electrical devices. Besides, the present method applies to the bonding of any surfaces with intrinsic or engineered surface nanoscopic structures as well. MDPI 2021-07-24 /pmc/articles/PMC8401537/ /pubmed/34443732 http://dx.doi.org/10.3390/nano11081901 Text en © 2021 by the authors. https://creativecommons.org/licenses/by/4.0/Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/).
spellingShingle Article
Guo, Jielin
Shih, Yu-Chou
Sheikhi, Roozbeh
You, Jiun-Pyng
Shi, Frank G.
Semiconductor Chip Electrical Interconnection and Bonding by Nano-Locking with Ultra-Fine Bond-Line Thickness
title Semiconductor Chip Electrical Interconnection and Bonding by Nano-Locking with Ultra-Fine Bond-Line Thickness
title_full Semiconductor Chip Electrical Interconnection and Bonding by Nano-Locking with Ultra-Fine Bond-Line Thickness
title_fullStr Semiconductor Chip Electrical Interconnection and Bonding by Nano-Locking with Ultra-Fine Bond-Line Thickness
title_full_unstemmed Semiconductor Chip Electrical Interconnection and Bonding by Nano-Locking with Ultra-Fine Bond-Line Thickness
title_short Semiconductor Chip Electrical Interconnection and Bonding by Nano-Locking with Ultra-Fine Bond-Line Thickness
title_sort semiconductor chip electrical interconnection and bonding by nano-locking with ultra-fine bond-line thickness
topic Article
url https://www.ncbi.nlm.nih.gov/pmc/articles/PMC8401537/
https://www.ncbi.nlm.nih.gov/pubmed/34443732
http://dx.doi.org/10.3390/nano11081901
work_keys_str_mv AT guojielin semiconductorchipelectricalinterconnectionandbondingbynanolockingwithultrafinebondlinethickness
AT shihyuchou semiconductorchipelectricalinterconnectionandbondingbynanolockingwithultrafinebondlinethickness
AT sheikhiroozbeh semiconductorchipelectricalinterconnectionandbondingbynanolockingwithultrafinebondlinethickness
AT youjiunpyng semiconductorchipelectricalinterconnectionandbondingbynanolockingwithultrafinebondlinethickness
AT shifrankg semiconductorchipelectricalinterconnectionandbondingbynanolockingwithultrafinebondlinethickness