Circuit Optimization Method to Reduce Disturbances in Poly-Si 1T-DRAM

A capacitorless one-transistor dynamic random-access memory device (1T-DRAM) is proposed to resolve the scaling problem in conventional one-transistor one-capacitor random-access memory (1T-1C-DRAM). Most studies on 1T-DRAM focus on device-level operation to replace 1T-1C-DRAM. To utilize 1T-DRAM as...

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Detalles Bibliográficos
Autores principales: Ha, Yejin, Shin, Hyungsoon, Sun, Wookyung, Park, Jisun
Formato: Online Artículo Texto
Lenguaje:English
Publicado: MDPI 2021
Materias:
Article
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC8539065/
https://www.ncbi.nlm.nih.gov/pubmed/34683260
http://dx.doi.org/10.3390/mi12101209

Internet

https://www.ncbi.nlm.nih.gov/pmc/articles/PMC8539065/
https://www.ncbi.nlm.nih.gov/pubmed/34683260
http://dx.doi.org/10.3390/mi12101209

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