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Current Rectification and Photo-Responsive Current Achieved through Interfacial Facet Control of Cu(2)O–Si Wafer Heterojunctions
[Image: see text] Conductive atomic force microscopy (C-AFM) was employed to perform conductivity measurements on a facet-specific Cu(2)O cube, octahedron, and rhombic dodecahedron and intrinsic Si {100}, {111}, and {110} wafers. Similar I–V curves to those recorded previously using a nanomanipulato...
Autores principales: | , , |
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Formato: | Online Artículo Texto |
Lenguaje: | English |
Publicado: |
American Chemical Society
2021
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Acceso en línea: | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC8614108/ https://www.ncbi.nlm.nih.gov/pubmed/34841063 http://dx.doi.org/10.1021/acscentsci.1c01067 |
Sumario: | [Image: see text] Conductive atomic force microscopy (C-AFM) was employed to perform conductivity measurements on a facet-specific Cu(2)O cube, octahedron, and rhombic dodecahedron and intrinsic Si {100}, {111}, and {110} wafers. Similar I–V curves to those recorded previously using a nanomanipulator were obtained with the exception of high conductivity for the Si {110} wafer. Next, I–V curves of different Cu(2)O–Si heterostructures were evaluated. Among the nine possible arrangements, Cu(2)O octahedron/Si {100} wafer and Cu(2)O octahedron/Si {110} wafer combinations show good current rectification behaviors. Under white light illumination, Cu(2)O cube/Si {110} wafer and Cu(2)O rhombic dodecahedron/Si {111} wafer combinations exhibit the largest degrees of photocurrent, so such interfacial plane-controlled semiconductor heterojunctions with light sensitivity can be applied to make photodetectors. Adjusted band diagrams are presented highlighting different interfacial band bending situations to facilitate or inhibit current flow for different Cu(2)O–Si junctions. More importantly, the observation of clear current-rectifying effects produced at the semiconductor heterojunctions with properly selected contacting faces or planes implies that novel field-effect transistors (FETs) can be fabricated using this design strategy, which should integrate well with current chip manufacturing processes. |
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