A Low-Jitter Harmonic-Free All-Digital Delay-Locked Loop for Multi-Channel Vernier TDC

This paper presents a low jitter All-Digital Delay-Locked Loop (ADDLL) with fast lock time and process immunity. A coarse locking algorithm is proposed to prevent harmonic locking with just a small increase in hardware resources. In order to effectively solve the dithering phenomenon after locking,...

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Detalles Bibliográficos
Autores principales: Tong, Jiyun, Wang, Sha, Zhang, Shuang, Zhang, Mengdi, Zhao, Ye, Zhao, Fazhan
Formato: Online Artículo Texto
Lenguaje:English
Publicado: MDPI 2021
Materias:
Article
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC8749538/
https://www.ncbi.nlm.nih.gov/pubmed/35009826
http://dx.doi.org/10.3390/s22010284

Internet

https://www.ncbi.nlm.nih.gov/pmc/articles/PMC8749538/
https://www.ncbi.nlm.nih.gov/pubmed/35009826
http://dx.doi.org/10.3390/s22010284

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