Logic Design and Power Optimization of Floating-Point Multipliers

Under IEEE-754 standard, for the current situation of excessive time and power consumption of multiplication operations in single-precision floating-point operations, the expanded boothwallace algorithm is used, and the partial product caused by booth coding is rounded and predicted with the symboli...

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Detalles Bibliográficos
Autores principales: Bai, Na, Li, Hang, Lv, Jiming, Yang, Shuai, Xu, Yaohua
Formato: Online Artículo Texto
Lenguaje:English
Publicado: Hindawi 2022
Materias:
Research Article
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC8759833/
https://www.ncbi.nlm.nih.gov/pubmed/35035464
http://dx.doi.org/10.1155/2022/6949846

Internet

https://www.ncbi.nlm.nih.gov/pmc/articles/PMC8759833/
https://www.ncbi.nlm.nih.gov/pubmed/35035464
http://dx.doi.org/10.1155/2022/6949846

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