Design and implementation of thermal collection networks in 3-D IC structures

The empirical affirmation in the electronics industry is that the power of chips per unit area is growing exponentially. The amount of heat generated is equal to the power; hence as power per unit area increases, so does the amount of heat generated within the chip. Thus, it necessary to mitigate the thermal problems of electronic systems. If not addressed or suppressed, thermal problems can lead to various issues including dielectric breakdown, electromigration, material creeping, unwanted chemical reactions, board warpage, drift in performance, and indirect heating. In this study, a dedicated thermal collection network (TCN) in the back end of the line area of an electronic chip was investigated. This network can help in creating a connection using a thermal through Silicon via (TTSV) to pump up the thermal energy to the heat-sink–fan assembly. Pre-empting heat from the sources could manage the thermal issues arising in chips as well as three-dimensional integrated circuit (3-D IC) structures. The finite-element method was the tool used for analysis. 31.62% of heat suction in TCNs of monolithic ICs, 11.36% in TCNs of 3-D IC structures, and 35.34% of heat suction in junctions of TTSVs compared with different approaches without the postulate used here. This procedure is expected to lead to a new path for redesigning electronic chips and 3-D IC structures.