4-Levels Vertically Stacked SiGe Channel Nanowires Gate-All-Around Transistor with Novel Channel Releasing and Source and Drain Silicide Process

In this paper, the fabrication and electrical performance optimization of a four-levels vertically stacked Si(0.7)Ge(0.3) channel nanowires gate-all-around transistor are explored in detail. First, a high crystalline quality and uniform stacked Si(0.7)Ge(0.3)/Si film is achieved by optimizing the ep...

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Detalles Bibliográficos
Autores principales: Cheng, Xiaohong, Li, Yongliang, Zhao, Fei, Chen, Anlan, Liu, Haoyan, Li, Chun, Zhang, Qingzhu, Yin, Huaxiang, Luo, Jun, Wang, Wenwu
Formato: Online Artículo Texto
Lenguaje:English
Publicado: MDPI 2022
Materias:
Article
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC8912512/
https://www.ncbi.nlm.nih.gov/pubmed/35269377
http://dx.doi.org/10.3390/nano12050889

Internet

https://www.ncbi.nlm.nih.gov/pmc/articles/PMC8912512/
https://www.ncbi.nlm.nih.gov/pubmed/35269377
http://dx.doi.org/10.3390/nano12050889

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