4-Levels Vertically Stacked SiGe Channel Nanowires Gate-All-Around Transistor with Novel Channel Releasing and Source and Drain Silicide Process

In this paper, the fabrication and electrical performance optimization of a four-levels vertically stacked Si(0.7)Ge(0.3) channel nanowires gate-all-around transistor are explored in detail. First, a high crystalline quality and uniform stacked Si(0.7)Ge(0.3)/Si film is achieved by optimizing the epitaxial growth process and a vertical profile of stacked Si(0.7)Ge(0.3)/Si fin is attained by further optimizing the etching process under the HBr/He/O(2) plasma. Moreover, a novel ACT@SG-201 solution without any dilution at the temperature of 40 °C is chosen as the optimal etching solution for the release process of Si(0.7)Ge(0.3) channel. As a result, the selectivity of Si to Si(0.7)Ge(0.3) can reach 32.84 with a signature of “rectangular” Si(0.7)Ge(0.3) extremities after channel release. Based on these newly developed processes, a 4-levels vertically stacked Si(0.7)Ge(0.3) nanowires gate-all-around device is prepared successfully. An excellent subthreshold slope of 77 mV/dec, drain induced barrier-lowering of 19 mV/V, I(on)/I(off) ratio of 9 × 10(5) and maximum of transconductance of ~83.35 μS/μm are demonstrated. However, its driven current is only ~38.6 μA/μm under V(DS) = V(GS) = −0.8 V due to its large resistance of source and drain (9.2 × 10(5) Ω). Therefore, a source and drain silicide process is implemented and its driven current can increase to 258.6 μA/μm (about 6.7 times) due to the decrease of resistance of source and drain to 6.4 × 10(4) Ω. Meanwhile, it is found that a slight increase of leakage after the silicide process online results in a slight deterioration of the subthreshold slope and I(on)/I(off) ratio. Its leakage performance needs to be further improved through the co-optimization of source and drain implantation and silicide process in the future.