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N-Type Nanosheet FETs without Ground Plane Region for Process Simplification

This paper proposes a simplified fabrication processing for nanosheet Field-Effect Transistors (FETs) part of beyond-3-nm node technology. Formation of the ground plane (GP) region can be replaced by an epitaxial grown doped ultra-thin (DUT) layer on the starting wafer prior to Si(x)/SiGe(1−x) stack...

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Detalles Bibliográficos
Autores principales: Lee, Khwang-Sun, Park, Jun-Young
Formato: Online Artículo Texto
Lenguaje:English
Publicado: MDPI 2022
Materias:
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC8954768/
https://www.ncbi.nlm.nih.gov/pubmed/35334724
http://dx.doi.org/10.3390/mi13030432