On-Chip Structures for F(max) Binning and Optimization †

Process variations during manufacturing lead to differences in the performance of the chips. In order to better utilize the performance of the chips, it is necessary to perform maximum operation frequency ([Formula: see text]) tests to place the chips into different speed bins. For most [Formula: see text] tests, significant efforts are put in place to reduce test cost and improve binning accuracy; e.g., our conference paper published in ICICM 2017 presents a novel binning sensor for low-cost and accurate speed binning. However, by promoting chips placed at the lower bins, because of conservative binning, into higher bins, the overall profit can greatly increase. Therefore, this paper, extended based on a conference paper, presents a novel and adaptive methodology for speed binning, in which the paths impacting the speed bin of a specific IC are identified and adapted by our proposed on-chip Binning Checker and Binning Adaptor. As a result, some parts at a bin margin can be promoted to higher bins. The proposed methodology can be used to optimize the [Formula: see text] yield of a digital circuit when it has redundant timing in clock tree, and it can be integrated into current [Formula: see text] tests with low extra cost. The proposed adaptive system has been implemented and validated on five benchmarks from ITC, ISCAS89, and OpenSPARCT2 core on 28 nm Altera FPGAs. Measurement results show that the number of higher bin chips is improved by 7–16%, and our cost analysis shows that the profit increase is between 1.18% and 3.04%.