Hysteretic temperature dependence of resistance controlled by gate voltage in LaAlO(3)/SrTiO(3) heterointerface electron system

For two-dimensional electron gas device applications, it is important to understand how electrical-transport properties are controlled by gate voltage. Here, we report gate voltage-controllable hysteresis in the resistance–temperature characteristics of two-dimensional electron gas at LaAlO(3)/SrTiO(3) heterointerface. Electron channels made of the LaAlO(3)/SrTiO(3) heterointerface showed hysteretic resistance–temperature behavior: the measured resistance was significantly higher during upward temperature sweeps in thermal cycling tests. Such hysteretic behavior was observed only after application of positive back-gate voltages below 50 K in the thermal cycle, and the magnitude of hysteresis increased with the applied back-gate voltage. To explain this gate-controlled resistance hysteresis, we propose a mechanism based on electron trapping at impurity sites, in conjunction with the strong temperature-dependent dielectric constant of the SrTiO(3) substrate. Our model explains well the observed gate-controlled hysteresis of the resistance–temperature characteristics, and the mechanism should be also applicable to other SrTiO(3)-based oxide systems, paving the way to applications of oxide heterostructures to electronic devices.