Scan Time Reduction of PLCs by Dedicated Parallel-Execution Multiple PID Controllers Using an FPGA

A programmable logic controller (PLC) executes a ladder diagram (LD) using input and output modules. An LD also has PID controller function blocks. It contains as many PID function blocks as the number of process parameters to be controlled. Adding more process parameters slows down PLC scan time. P...

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Detalles Bibliográficos
Autores principales: Dhanabalan, Gnanasekaran, Tamil Selvi, Sankar, Mahdal, Miroslav
Formato: Online Artículo Texto
Lenguaje:English
Publicado: MDPI 2022
Materias:
Article
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC9230057/
https://www.ncbi.nlm.nih.gov/pubmed/35746367
http://dx.doi.org/10.3390/s22124584

Internet

https://www.ncbi.nlm.nih.gov/pmc/articles/PMC9230057/
https://www.ncbi.nlm.nih.gov/pubmed/35746367
http://dx.doi.org/10.3390/s22124584

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