Device and Circuit Analysis of Double Gate Field Effect Transistor with Mono-Layer WS(2)-Channel at Sub-2 nm Technology Node

In this work, WS(2) was adopted as a channel material among transition metal dichalcogenides (TMD) materials that have recently been in the spotlight, and the circuit power performance (power consumption, operating frequency) of the monolayer WS(2) field-effect transistor with a double gate structure (DG WS(2)-FET) was analyzed. It was confirmed that the effective capacitance, which is circuit power performance, was greatly changed by the extrinsic capacitance components of DG WS(2)-FET, and the spacer region length (L(SPC)) and dielectric constant (K(SPC)) values of the spacer that could affect the extrinsic capacitance components were analyzed to identify the circuit power performance. As a result, when L(SPC) is increased by 1.5 nm with the typical spacer material (K(SPC) = 7.5), increased operating speed (+4.9%) and reduced active power (–6.8%) are expected. In addition, it is expected that the spacer material improvement by developing the low-k spacer from K(SPC) = 7.5 to K(SPC) = 2 at typical L(SPC) = 8 nm can increase the operating speed by 36.8% while maintaining similar active power consumption. Considering back-end-of-line (BEOL), the change in circuit power performance according to wire length was also analyzed. From these results, it can be seen that reducing the capacitance components of the extrinsic region is very important for improving the circuit power performance of the DG WS(2)-FET.