Effects of JFET Region Design and Gate Oxide Thickness on the Static and Dynamic Performance of 650 V SiC Planar Power MOSFETs

650 V SiC planar MOSFETs with various JFET widths, JFET doping concentrations, and gate oxide thicknesses were fabricated by a commercial SiC foundry on two six-inch SiC epitaxial wafers. An orthogonal [Formula: see text] layout was used for the 650 V SiC MOSFETs to reduce the ON-resistance. The dev...

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Detalles Bibliográficos
Autores principales: Zhu, Shengnan, Liu, Tianshi, Fan, Junchong, Maddi, Hema Lata Rao, White, Marvin H., Agarwal, Anant K.
Formato: Online Artículo Texto
Lenguaje:English
Publicado: MDPI 2022
Materias:
Article
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC9457212/
https://www.ncbi.nlm.nih.gov/pubmed/36079378
http://dx.doi.org/10.3390/ma15175995

Internet

https://www.ncbi.nlm.nih.gov/pmc/articles/PMC9457212/
https://www.ncbi.nlm.nih.gov/pubmed/36079378
http://dx.doi.org/10.3390/ma15175995

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