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A Study on the Sub-5 nm Nano-Step Height Reference Materials Fabricated by Atomic Layer Deposition Combined with Wet Etching
Nano-steps, as classical nano-geometric reference materials, are very important for calibrating measurements in the semiconductor industry; therefore, controlling the height of nano-steps is critical for ensuring accurate measurements. Accordingly, in this study nano-steps with heights of 1, 2, 3 an...
Autores principales: | , , , , , , , , , , , |
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Formato: | Online Artículo Texto |
Lenguaje: | English |
Publicado: |
MDPI
2022
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Materias: | |
Acceso en línea: | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC9506470/ https://www.ncbi.nlm.nih.gov/pubmed/36144077 http://dx.doi.org/10.3390/mi13091454 |
Sumario: | Nano-steps, as classical nano-geometric reference materials, are very important for calibrating measurements in the semiconductor industry; therefore, controlling the height of nano-steps is critical for ensuring accurate measurements. Accordingly, in this study nano-steps with heights of 1, 2, 3 and 4 nm were fabricated with good morphology using atomic layer deposition (ALD) combined with wet etching. The roughness of the fabricated nano-steps was effectively controlled by utilizing the three-dimensional conformal ALD process. Moreover, the relationship between the surface roughness and the height was studied using a simulation-based analysis. Essentially, roughness control is crucial in fabricating nano-steps with a critical dimension of less than 5 nm. In this study, the minimum height of a nano-step that was successfully achieved by combining ALD and wet etching was 1 nm. Furthermore, the preconditions for quality assurance for a reference material and the influencing factors of the fabrication method were analyzed based on the 1 nm nano-step sample. Finally, the fabricated samples were used in time-dependent experiments to verify the optimal stability of the nano-steps as reference materials. This research is instructive to fabricate nano-geometric reference materials to within 5 nm in height, and the proposed method can be easily employed to manufacture wafer-sized step height reference materials, thus enabling its large-scale industrial application for in-line calibration in integrated circuit production lines. |
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