Sensitivity of Inner Spacer Thickness Variations for Sub-3-nm Node Silicon Nanosheet Field-Effect Transistors

The inner spacer thickness (T(IS)) variations in sub-3-nm, node 3-stacked, nanosheet field-effect transistors (NSFETs) were investigated using computer-aided design simulation technology. Inner spacer formation requires a high selectivity of SiGe to Si, which causes inevitable T(IS) variation (ΔT(IS)). The gate length (L(G)) depends on the T(IS). Thus, the DC/AC performance is significantly affected by ΔT(IS). Because the effects of ΔT(IS) on the performance depend on which inner spacer is varied, the sensitivities of the performance to the top, middle, and bottom (T, M, and B, respectively) ΔT(IS) should be studied separately. In addition, the source/drain (S/D) recess process variation that forms the parasitic bottom transistor (tr(pbt)) should be considered with ΔT(IS) because the gate controllability over tr(pbt) is significantly dependent on ΔT(IS,B). If the S/D recess depth (T(SD)) variation cannot be completely eliminated, reducing ΔT(IS,B) is crucial for suppressing the effects of tr(pbt). It is noteworthy that reducing ΔT(IS,B) is the most important factor when the T(SD) variation occurs, whereas reducing ΔT(IS,T) and ΔT(IS,M) is crucial in the absence of T(SD) variation to minimize the DC performance variation. As the T(IS) increases, the gate capacitance (C(gg)) decreases owing to the reduction in both parasitic and intrinsic capacitance, but the sensitivity of C(gg) to each ΔT(IS) is almost the same. Therefore, the difference in performance sensitivity related to AC response is also strongly affected by the DC characteristics. In particular, since T(SD) of 5 nm increases the off-state current (I(off)) sensitivity to ΔT(IS,B) by a factor of 22.5 in NFETs, the ΔT(IS,B) below 1 nm is essential for further scaling and yield enhancement.