Effect of high-pressure D(2) and H(2) annealing on LFN properties in FD-SOI pTFET

Tunneling field-effect transistors (TFETs) are a promising candidate for the next generation of low-power devices, but their performance is very sensitive to traps near the tunneling junction. This study investigated the effects of high-pressure deuterium (D(2)) annealing and hydrogen (H(2)) annealing on the electrical performance and low-frequency noise (LFN) of a fully depleted silicon-on-insulator p-type TFET. Without high-pressure annealing, the typical noise power spectral density exhibited two Lorentzian spectra that were affected by fast and slow trap sites. With high-pressure annealing, the interface trap density related to fast trap sites was reduced. The passivation of traps near the tunneling junction indicates that high-pressure H(2) and D(2) annealing improves the electrical performance and LFN properties, and it may become a significant and necessary step for realizing integrated TFET technology in the future.