Steep-Slope and Hysteresis-Free MoS(2) Negative-Capacitance Transistors Using Single HfZrAlO Layer as Gate Dielectric

An effective way to reduce the power consumption of an integrated circuit is to introduce negative capacitance (NC) into the gate stack. Usually, negative-capacitance field-effect transistors (NCFETs) use both a negative-capacitance layer and a positive-capacitance layer as the stack gate, which is...

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Detalles Bibliográficos
Autores principales: Tao, Xinge, Liu, Lu, Xu, Jingping
Formato: Online Artículo Texto
Lenguaje:English
Publicado: MDPI 2022
Materias:
Article
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC9781945/
https://www.ncbi.nlm.nih.gov/pubmed/36558206
http://dx.doi.org/10.3390/nano12244352

Internet

https://www.ncbi.nlm.nih.gov/pmc/articles/PMC9781945/
https://www.ncbi.nlm.nih.gov/pubmed/36558206
http://dx.doi.org/10.3390/nano12244352

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