An Automatic Detection Method for Cutting Path of Chips in Wafer

HIGHLIGHTS: Cutting path Planning System for wafer images without Mark points in different imaging states. Use the interlayer in the chip region as an auxiliary location to determine the cutting path. The determined cutting path is located in the middle of the streets, away from the chip region. ABSTRACT: Microscopic imaging is easily affected by the strength of illumination, and the chip surface qualities of different wafers are different. Therefore, wafer images have defects such as uneven brightness distribution, obvious differences in chip region characteristics, etc., which affect the positioning accuracy of the wafer cutting path. For this reason, this thesis proposes an automatic chip-cutting path-planning method in the wafer image of the Glass Passivation Parts (GPPs) process without a mark. First, the wafer image is calibrated for brightness. Then, the template matching algorithm is used to determine the chip region and the center of gravity position of the chip region. We find the position of the geometric feature (interlayer) in the chip region, and the interlayer is used as an auxiliary location to determine the final cutting path. The experiment shows that the image quality can be improved, and chip region features can be highlighted when preprocessing the image with brightness calibration. The results show that the average deviation of the gravity coordinates of the chip region in the x direction is 2.82 pixels. We proceeded by finding the interlayer in the chip region, marking it with discrete points, and using the improved Random Sample Consensus (RANSAC) algorithm to remove the abnormal discrete points and fit the remaining discrete points. The average fitting error is 0.8 pixels, which is better than the least squares method (LSM). The cutting path location algorithm proposed in this paper can adapt to environmental brightness changes and different qualities of chips, accurately and quickly determine the cutting path, and improve the chip cutting yield.