Multiple Retest Systems for Screening High-Quality Chips

In this study, we develop a digital integrated circuit testing model (DITM) based on a statistical simulation method to evaluate the test quality and yield of integrated circuit products. This model can be used to quantify the characteristics of the device under test (DUT) and simulate the effect of the test guardband (TGB) on test results during testing. The complexity and functionality of integrated circuits have continued to increase over the past two decades. Moreover, the development in speed of automated test equipment (ATE), e.g., OTA or overall timing accuracy, according to the ITRS report, lags behind the progress of semiconductor manufacturing. Hence, using existing instruments and tools to select zero-defect products would be a considerable challenge for suppliers due to the slow development of the testing technology. We propose a new scheme of using multiple retest systems (MRSs) to improve the yield while maintaining the desired quality to address the product quality requirements of consumers. We also use a set of parameters from IRDS 2021 (International Roadmap for Devices and Systems 2021) to estimate the future test yield (Y(t)) and test quality through DITM calculations. MRS results showed that the test yield (Y(t)) can be improved while achieving the expected quality. MRSs not only improve the performance of the tester but also demonstrate effective performance in the yield improvement of high-quality products. This approach enables high-quality, high-yield chip delivery, and significantly increases the overall profit of the company.