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A 21.4 pW Subthreshold Voltage Reference with 0.020 %/V Line Sensitivity Using DIBL Compensation
This paper presents an ultra-low-power voltage reference designed in 180 nm CMOS technology. To achieve near-zero line sensitivity, a two-transistor (2-T) voltage reference is biased with a current source to cancel the drain-induced barrier-lowering (DIBL) effect of the 2-T core, thus improving the...
| Autores principales: | , , |
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| Formato: | Online Artículo Texto |
| Lenguaje: | English |
| Publicado: |
MDPI
2023
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| Materias: | |
| Acceso en línea: | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC9963272/ https://www.ncbi.nlm.nih.gov/pubmed/36850459 http://dx.doi.org/10.3390/s23041862 |